Shows Trojan-Resilient NTT Protects Post-Cryptography Against Control and Timing Faults

Researchers are increasingly focused on securing Number Theoretic Transforms (NTT), a critical component underpinning lattice-based post-quantum cryptography algorithms like Kyber, Dilithium and NTRU, against evolving hardware threats. Rourab Paul from Shiv Nadar University, Krishnendu Guha from University College Cork, and Amlan Chakrabarti from University of Calcutta demonstrate a novel NTT architecture designed to detect and mitigate both control flow and timing faults introduced by hardware Trojans and soft analytical side-channel attacks. This work is significant because it addresses a growing vulnerability in post-quantum cryptographic implementations, where compromised control signals pose a particularly impactful and low-cost attack vector, potentially disrupting entire computations, unlike localised data faults. Their secure NTT, implemented and simulated on an Artix-7 FPGA, offers adaptive fault mitigation with minimal performance and area overheads, representing a substantial step towards resilient cryptographic hardware.

Protecting NTT Architectures from Control Signal Manipulation and Hardware Trojans requires robust security measures

Scientists have developed a secure Number Theoretic Transform (NTT) architecture designed to safeguard against increasingly sophisticated hardware attacks targeting post-quantum cryptographic systems. This research addresses vulnerabilities stemming from both side-channel attacks and the insertion of malicious hardware Trojans, which can disrupt critical control signals and introduce unconventional delays within the NTT circuitry.
The team achieved a design capable of detecting these disruptions and implementing adaptive fault mitigation techniques, crucial for the reliable operation of lattice-based cryptography schemes like Kyber, Dilithium, and NTRU. The study reveals a novel approach to NTT implementation, focusing on the protection of control signals, which are particularly susceptible to Trojan attacks due to their broad impact on computation.

Unlike attacks targeting data signals that cause localised errors, compromising a control signal can bypass entire computational sequences. Researchers constructed a fault detection and correction methodology, extensively simulating and implementing their Secure NTT on an Artix-7 FPGA. This implementation demonstrates the ability to efficiently identify faults, whether unintentional due to aging or intentionally introduced by hardware Trojans, with a high degree of accuracy.

Experiments show the Secure NTT’s fault detection modules can effectively identify and correct errors across various Kyber variants. The work establishes that this enhanced security is achieved with only modest increases in area and timing overheads, making it a practical solution for resource-constrained platforms.

This breakthrough is particularly relevant given the projected 11 billion USD market for FPGAs by 2027, and the associated increase in risk from globalised supply chains and potential hardware Trojan insertion at multiple stages of the manufacturing process. The research opens avenues for building more resilient cryptographic systems, essential for securing future high-speed data communication infrastructure.

By focusing on control flow integrity and unconventional delay detection, this study provides a critical step towards protecting sensitive data from both passive observation via Soft Analytical Side Channel Attacks and active manipulation through hardware Trojans. The research addresses vulnerabilities arising from unconventional delays and control-flow disruptions potentially introduced by hardware Trojans, which pose a greater risk to control signals than data signals.

This work pioneers a system capable of detecting these faults and mitigating their impact through an adaptive fault-correction methodology. Researchers implemented the Secure NTT on an Artix-7 FPGA, conducting extensive simulations with various Kyber variants to validate its effectiveness. The study employed a fault detection and correction module designed to identify faults, whether unintentional due to aging or intentional insertion of hardware Trojans, with a high success rate.

This approach achieves fault detection by monitoring for deviations from expected timing and control flow within the NTT computation. The NTT significantly reduces the computational complexity of polynomial multiplication from O(n²) to O(n log n), accelerating PQC schemes on platforms such as FPGAs. Scientists harnessed this acceleration for high-speed data communication infrastructure, while simultaneously addressing the inherent vulnerabilities of NTT to side-channel attacks and hardware Trojans.

The team investigated potential attack vectors including design-time, foundry-level, and post-design bitstream manipulation, recognising that malicious CAD tools could bypass security checks. Experiments focused on detecting unconventional delays and control-flow disruptions, crucial indicators of both unintentional hardware degradation and malicious Trojan activity.

Prior work primarily targeted data signal protection, but this study concentrated on control signals due to their greater impact. The team’s methodology builds upon existing fault detection techniques, such as recomputing multiplication results using the Recomputation with Negate Operands (RENO) technique, but extends it to encompass control flow integrity. This innovative approach introduces only modest area and time overheads while significantly enhancing the security of the NTT implementation.

Secure NTT architecture mitigates hardware Trojan attacks with negligible performance impact through advanced detection methods

Scientists have developed a secure Number Theoretic Transform (NTT) architecture designed to detect and mitigate unconventional delays, control-flow disruptions, and Soft Analytical Side Channel Attacks (SASCA) in lattice-based Post-Quantum Cryptography (PQC) algorithms. The research addresses vulnerabilities stemming from hardware Trojans that can manipulate control signals, potentially disrupting critical computations.

Experiments reveal that the proposed Secure NTT, implemented on an Artix-7 FPGA, can efficiently detect faults, whether unintentional or maliciously introduced, with a high success rate. The team measured the performance of their Secure NTT on an Artix-7 FPGA with 5 pipeline stages, achieving fault detection without incurring any timing overhead.

Data shows that the implementation overhead of the fault detection and correction modules is minimal, remaining competitive with existing NTT solutions. The NTT algorithm primarily consists of memory read, arithmetic operations, and memory write stages, with arithmetic operations masked using Local Masking at each clock cycle.

Unintentional delays and control-flow integrity are addressed using a Clock Cycle Counter and Control Flow Integrity module, respectively. Results demonstrate that the proposed NTT requires log₂n × n/2 clock cycles for operation with n = 256 and a pipeline depth of 5, totaling 1028 clock cycles. The Control Flow Integrity is maintained through a 4-bit Control Status Register (CSR) which generates input control signals for sub-components, shifting its bits at each clock cycle like a right shift register.

Measurements confirm that the CSR controls all sub-components by generating necessary control signals, with specific signals derived directly from the CSR or its inverse. Tests prove the effectiveness of a Right Shift Register (RSR), independent of the main NTT logic, in monitoring control flow integrity.

The RSR’s third most significant bit mirrors the state of the read enable signal, providing a secondary check against tampering. The breakthrough delivers a robust NTT architecture capable of safeguarding PQC implementations against a range of hardware and software attacks, paving the way for more secure cryptographic systems.

Detecting and mitigating faults in post-quantum cryptographic NTT implementations is crucial for secure deployment

Researchers have developed a secure Number Theoretic Transform (NTT) architecture designed to defend against side-channel attacks and hardware Trojan threats in lattice-based post-quantum cryptography (PQC) algorithms. The core innovation lies in a fault detection methodology that identifies unconventional delays and control-flow disruptions, alongside a corresponding fault mitigation strategy.

This secure NTT implementation, tested with Kyber variants, demonstrates the ability to efficiently detect both unintentional and intentionally introduced faults caused by hardware Trojans, achieving a high success rate with only modest increases in area and timing overhead. The proposed architecture employs Local Masking for arithmetic operations, a Clock Cycle Counter (CCC) to monitor timing, and Control Flow Integrity (CFI) to ensure correct execution sequencing.

The CFI mechanism utilizes a Control Status Register (CSR) to govern control signals for NTT subcomponents, preventing malicious alteration of the computational process. Implementation on an Artix-7 FPGA with a five-pipeline stage design achieved fault detection without incurring timing penalties, and the fault detection and correction modules exhibited minimal overhead compared to existing NTT solutions.

The authors acknowledge that the security assessment is currently limited to specific attack models and FPGA implementations. Future work will focus on extending the fault detection capabilities to cover a broader range of potential threats and exploring implementation on alternative hardware platforms to enhance the robustness and adaptability of the secure NTT architecture.