SECQAI has successfully taped out its SE01 “Q-Locked” Trusted Platform Module (TPM) system-on-chip, fabricated with TSMC’s 22nm process, to advance secure computation. This CHERI ISA V9-based TPM incorporates hardware acceleration for Post-Quantum Cryptography (PQC) algorithms aligned with NIST standards and is designed towards FIPS 140-3 compliance. Pioneered with technology from the University of Cambridge’s Department of Computer Science and Technology, the Q-Locked TPM addresses the approximately 70% of Common Vulnerabilities and Exposures (CVEs) stemming from memory safety issues, offering scalable, quantum-resistant security for critical infrastructure and consumer devices.
CHERI Architecture Enables Memory Safety
SECQAI recently “taped out” its SE01 “Q-Locked” Trusted Platform Module (TPM) using TSMC’s 22nm process. This chip is significant because it implements the Capability Hardware Enhanced RISC Instructions (CHERI) ISA v9 architecture. Crucially, CHERI dramatically improves memory safety – research indicates around 70% of Common Vulnerabilities and Exposures (CVEs) stem from memory-related issues. By building this protection into the semiconductor itself, SECQAI aims to scale security across infrastructure and reduce the overall attack surface.
The core innovation lies in CHERI’s capability-based approach. Standard processors access memory directly; CHERI introduces “capabilities” – essentially, secure tokens granting specific access rights. New instructions handle these capabilities for loads, stores, and manipulations, preventing unauthorized memory access. This isn’t simply software patching; it’s a fundamental redesign leveraging the RISC-V ISA, spearheaded by the University of Cambridge and SRI International, for inherently safer computation.
Beyond memory safety, the Q-Locked TPM is designed for the post-quantum era. It accelerates the deployment of NIST-approved Post Quantum Cryptography (PQC) algorithms (FIPS 203, 204, and 205). This hardware acceleration is vital, as quantum computers pose a threat to current encryption methods. SECQAI’s chip offers OEMs a future-proof solution, combining robust memory safety with resilience against advanced computational attacks – a key step in securing critical infrastructure.
Accelerating Post-Quantum Cryptography Adoption
SECQAI has successfully “taped out” its SE01 “Q-Locked” TPM chip with TSMC using a 22nm process, marking a significant step toward commercially available, quantum-resistant security. This Trusted Platform Module (TPM) incorporates the Capability Hardware Enhanced RISC Instructions (CHERI) ISA v9 architecture, fundamentally improving memory safety – addressing roughly 70% of Common Vulnerabilities and Exposures (CVEs) according to Microsoft research. The design prioritizes a “secure by design” approach, hardening devices at the hardware level against increasingly sophisticated attacks.
The Q-Locked TPM isn’t just about memory safety; it’s engineered to accelerate Post-Quantum Cryptography (PQC) implementations. Specifically, the chip supports NIST-approved algorithms (FIPS 203, 204, and 205), future-proofing systems against the threat of quantum computers breaking current encryption standards. This hardware acceleration is crucial as transitioning to PQC requires substantial computational resources, and SECQAI’s chip aims to ease that burden for Original Equipment Manufacturers (OEMs).
SECQAI’s achievement is part of a broader initiative, as the company was one of ten innovators selected by DIANA, a NATO-backed organization focused on dual-use security technologies. This highlights the strategic importance of securing critical infrastructure. By combining memory safety with PQC acceleration, SECQAI aims to deliver a foundational security element for servers, AI infrastructure, and consumer devices, addressing vulnerabilities from the ground up and enabling widespread adoption of more secure computing.
