Post-Quantum Cryptography with High-Speed Polynomial Multipliers

The quest for secure communication in the era of quantum computing has led to significant advancements in post-quantum cryptography (PQC). Code-based PQC schemes, such as Hamming Quasi-Cyclic (HQC) and Bit Flipping Key Encapsulation (BIKE), have emerged as promising candidates. However, their implementation requires efficient sparse polynomial multiplication accelerators. Researchers from Villanova University have proposed two novel high-throughput sparse polynomial multiplication accelerators (HSPAs) that outperform existing designs.

Researchers at Villanova University have designed two novel High-Throughput Sparse Polynomial multiplication Accelerators (HSPA) for code-based post-quantum cryptography schemes, such as Hamming Quasi-Cyclic (HQC) and Bit Flipping Key Encapsulation (BIKE). The accelerators employ a parallel segment-based accumulation approach or a permutating with power method to execute sparse polynomial multiplication efficiently. Implemented on FPGA platforms, the proposed HSPAs demonstrate superior performance compared to existing memory-based designs, achieving significant reductions in read delay product for HQC and BIKE. These advancements are crucial for the adoption of code-based PQC in various applications.

The increasing attention paid to code-based post-quantum cryptography (PQC) schemes has led to the selection of Hamming Quasi-Cyclic (HQC) and Bit Flipping Key Encapsulation (BIKE) as fourth-round candidates in the National Institute of Standards and Technology (NIST) PQC standardization process. However, sparse polynomial multiplication is a critical component for HQC and BIKE, and high-performance sparse polynomial multipliers are rarely reported in the literature due to their high dimensionality and sparsity.

In this context, researchers from Villanova University have proposed two novel High-Throughput Sparse Polynomial multiplication Accelerators (HSPA) for the mentioned code-based PQC schemes. The accelerators were designed based on two different implementation strategies, targeting potential applications with varying resource availability. One accelerator deploys a memory-based structure for computation, while the other does not require memory usage.

The proposed HSPAs are the result of three layers of coherent interdependent efforts. Firstly, two implementation strategies were proposed to execute the targeted sparse polynomial multiplication: a new parallel segment-based accumulation (PSA) approach and an novel permutating with power (PWP)-based method. Secondly, the proposed hardware accelerators were presented with detailed structural descriptions. Finally, field-programmable gate array (FPGA)-based implementation was showcased to demonstrate the superior performance of the proposed accelerators.

One accelerator deploys a memory-based structure for computation, while the other does not require memory usage. The proposed HSPAs result from three layers of coherent interdependent efforts: proposing implementation strategies, presenting hardware accelerators with detailed structural descriptions, and showcasing FPGA-based implementation to demonstrate superior performance.

The proposed accelerators were designed to target potential applications with varying resource availability. One accelerator was designed for HQC, while the other was designed for BIKE. The HSPAs were implemented using FPGAs, allowing for a proper efficiency comparison. For instance, the proposed accelerator using a memory-based structure had 5684 and 8025 less read delay product (ADP) than existing memory-based designs for n=17669 and ω=75 HQC and n=12323 and ω=142 BIKE, respectively.

Implementing high-throughput sparse polynomial multiplication accelerators is a critical component for code-based post-quantum cryptography schemes. In this context, researchers from Villanova University have proposed two novel implementation strategies: parallel segment-based accumulation (PSA) and permutating with power (PWP)-based methods.

The PSA approach involves executing the targeted sparse polynomial multiplication in parallel segments, which allows for high-throughput computation. The PWP-based method involves permutating the polynomials involved in the computation using powers of 2, which reduces the computational complexity.

Both implementation strategies were proposed to target potential applications with varying resource availability. One strategy was designed for HQC, while the other was designed for BIKE. The proposed accelerators were implemented using FPGAs, which allowed for a proper comparison of their efficiency.

The increasing attention paid to code-based post-quantum cryptography schemes has led to the selection of Hamming Quasi-Cyclic (HQC) and Bit Flipping Key Encapsulation (BIKE) as fourth-round candidates in the National Institute of Standards and Technology (NIST) PQC standardization process. However, sparse polynomial multiplication is a critical component for HQC and BIKE, and high-performance sparse polynomial multipliers are rarely reported in the literature due to their high dimensionality and sparsity.

In this context, researchers from Villanova University have proposed two novel High-Throughput Sparse Polynomial multiplication Accelerators (HSPA) for the mentioned code-based PQC schemes. The accelerators were designed based on two different implementation strategies, targeting potential applications with varying resource availability. One accelerator deploys a memory-based structure for computation, while the other does not require memory usage.

The proposed HSPAs are the result of three layers of coherent interdependent efforts: proposing implementation strategies, presenting hardware accelerators with detailed structural descriptions, and showcasing FPGA-based implementation to demonstrate superior performance. The results demonstrate the efficiency of the proposed designs, which can be used for code-based post-quantum cryptography schemes.