Parity Architecture Enhances Spin Qubits for Quantum Computing, Study Finds

Scientists from Parity Quantum Computing Germany GmbH, Institute for Theoretical Physics University of Innsbruck, JARAFIT Institute for Quantum Information Forschungszentrum Jülich GmbH, and ARQUE Systems GmbH are conducting research on the Scalable Parity Architecture with a Shuttling-Based Spin Qubit Processor. The project explores the potential of a two-dimensional square-lattice geometry for semiconductor spin qubits. The team has developed sequences of spin shuttling and quantum gates that implement the Parity Quantum Approximate Optimization Algorithm (QAOA) on a lattice. The Parity Architecture is significant as it allows for the creation of connectivity between qubits in two dimensions, essential for error-corrected quantum computing.

What is the Scalable Parity Architecture with a Shuttling-Based Spin Qubit Processor?

The Scalable Parity Architecture with a Shuttling-Based Spin Qubit Processor is a research project conducted by a team of scientists from Parity Quantum Computing Germany GmbH, Institute for Theoretical Physics University of Innsbruck, JARAFIT Institute for Quantum Information Forschungszentrum Jülich GmbH, and ARQUE Systems GmbH. The research is motivated by the potential of a two-dimensional square-lattice geometry for semiconductor spin qubits. The team explores the realization of the Parity Architecture with quantum dots (QDs), which are part of the effort to develop architectures that enhance the use of spin qubits for quantum computing.

The research presents sequences of spin shuttling and quantum gates that implement the Parity Quantum Approximate Optimization Algorithm (QAOA) on a lattice constructed of identical unit cells. The circuit depth is independent of the problem Hamiltonian and the system size. The team also develops an error model that includes a general description of the shuttling errors as a function of the probability distribution function of the valley splitting. They estimate the errors during one round of Parity QAOA, mainly limited by the valley splitting.

What is the Significance of the Parity Architecture?

The Parity Architecture is significant in the development of spin qubits as it allows for the creation of connectivity between qubits in two dimensions. This is essential for error-corrected quantum computing. The Parity Architecture also makes it possible to advance the performance of spin qubits. In the Parity Architecture, the logical state of the quantum computer is encoded by physical qubits that represent the parity of the logical spins.

While this encoding introduces a qubit overhead, it removes the requirement for long-distance interactions and the redundant information allows for quantum error mitigation and partial quantum error correction. It also enables the execution of the Parity Quantum Approximate Optimization Algorithm (QAOA) and reduces the circuit depth of cornerstone algorithms such as the quantum Fourier transform.

What is the Quantum Approximate Optimization Algorithm (QAOA)?

The Quantum Approximate Optimization Algorithm (QAOA) is a gate-based algorithm for solving combinatorial optimization problems on a digital quantum computer. It is inspired by adiabatic quantum computing, where a quantum state is evolved adiabatically under a Hamiltonian representing the cost function of the optimization problem in order to approximate its ground state.

In QAOA, adiabatic time evolution is replaced by an alternating sequence of parameterized small-angle rotations corresponding to a problem and driver Hamiltonian respectively. The parameters are then optimized in a quantum-classical feedback loop. The QAOA has been demonstrated on existing quantum hardware and may be a suitable candidate to prove a quantum advantage for nontrivial problems with a few hundreds of qubits and gate fidelity below the error correction threshold.

How Does Spin Shuttling Work in Quantum Computing?

Spin shuttling in quantum computing involves coherently moving the qubits between sites with different functionality on the chip on demand. Shuttling can be realized either in the conveyor mode, where a sliding potential well smoothly displaces the qubit, or as a bucket brigade by coherent tunneling between adjacent QDs.

While the latter variant requires a high degree of individual control, conveyor-mode shuttling with potentials formed by dedicated gates are showing promising success. In silicon heterostructures, the degenerate conduction band minima lead to an additional pseudo-spin, the valley degree of freedom, whose splitting is determined by the microscopic properties of the interface. Local minima of the valley splitting can be a major challenge for conveyor-mode shuttling, however, their occurrence can be reduced by engineering the semiconductor heterostructure or adjusting shuttling trajectories.

What are the Challenges and Future Prospects of Spin-Based Quantum Computing?

Spin-based quantum computing, while promising, faces several challenges. These include environmental electric noise, crosstalk and residual exchange interaction within dense arrays of qubits, and the demanding space requirements of the voltage gates and control electronics.

However, the use of spin shuttling and the development of the Parity Architecture offer potential solutions to these challenges. The research team expects spin qubits to prove an efficient implementation of the Parity Architecture since their native gates naturally fit the demands for Parity QAOA and thus require little additional transpilation. Different strategies are currently under investigation for realizing a two-dimensional lattice of spin qubits, which perfectly suits the Parity Architecture.