Oxford Quantum Circuits (OQC) has unveiled a groundbreaking wafer-scale packaging architecture capable of housing over 500 superconducting qubits on a single 3-inch die, a major step towards building practical, fault-tolerant quantum computers. Released as a preprint on arXiv on February 16, 2026, the research demonstrates large-scale qubit integration without compromising performance – a critical hurdle in quantum processor development. The innovative design mitigates error channels through features like a dense pillar array and simulation-driven loss budgeting, achieving a median T₁ of 97 μs and a median T₂e of 129 μs across measured qubits. As OQC advances towards scalable processors, this architecture provides a blueprint for tackling the engineering challenges of integrating the millions of qubits potentially needed for error correction, proving that “scaling the package does not degrade qubit performance.”
Wafer-Scale Architecture Maintains 97μs T₁ Coherence for 500+ Qubits
The London-based firm detailed a wafer-scale packaging architecture capable of supporting this dense array, a critical step toward building the millions of qubits anticipated for fault-tolerant quantum computers. This isn’t simply about cramming more qubits into a small space; the challenge lies in maintaining their delicate quantum states. OQC’s design directly addresses potential error channels introduced by large-scale packaging, such as microwave loss and thermal constraints. Key to the architecture is a superconducting cavity structure featuring a “dense pillar array to push box modes above qubit and resonator frequency bands,” ensuring signal integrity.
Rigorous simulation and modelling were employed, including “simulation-driven loss budgeting using energy participation ratio (EPR) methods” to quantify potential signal degradation. Crucially, experimental validation confirms minimal performance impact; the team measured a median T₁ coherence time of approximately 97 μs across 105 qubits. Beyond integration, the wafer-scale approach functions as a powerful manufacturing tool.
OQC demonstrated the ability to analyze coherence distributions across the entire wafer by measuring a substantial number of qubits – O(100) – simultaneously. “Identifying minimum and maximum coherence values with high confidence requires large sample sizes,” the researchers found, highlighting the value of this high-throughput metrology for iterative research and development. Thermal modelling also indicates the system is compatible with existing cryogenic infrastructure, predicting a mixing chamber heat load of around 3 μW, even with a fully wired 504-qubit configuration. OQC concluded that wafer-scale packaging supporting >500 superconducting qubits can be realised while maintaining high coherence and measurement performance.
Energy Participation Ratio (EPR) Mitigates Packaging-Induced Microwave Losses
The pursuit of scalable quantum computing demands increasingly dense qubit architectures, but simply increasing qubit count introduces significant engineering hurdles. Beyond the challenges of controlling and connecting hundreds of qubits, maintaining their delicate quantum states is paramount – and packaging plays a critical role. Oxford Quantum Circuits (OQC) has demonstrated a wafer-scale packaging architecture designed to address these issues, specifically focusing on minimizing microwave losses that can degrade qubit performance. Finite-element modelling of differential thermal contraction further ensures the mechanical stability of the system during the extreme cooling required for superconducting qubits.
Crucially, OQC’s approach isn’t just theoretical; experimental validation confirms minimal impact on qubit coherence. Readout error remained low, with a median of just 2.5% – representing 97.5% fidelity – across 54 qubits. “Finite-element simulations indicate that packaging-induced loss limits remain well above measured coherence times, confirming that device performance is primarily material-limited rather than packaging-limited,” demonstrating the effectiveness of the EPR-guided design. This suggests that further improvements in qubit materials themselves will yield the most significant gains, rather than being hampered by packaging limitations.
High-Throughput Metrology Enables Coherence Mapping of Large Qubit Ensembles
Oxford Quantum Circuits (OQC) is pioneering a new approach to quantum processor development, focusing on the detailed characterisation of large qubit arrays facilitated by wafer-scale packaging. Beyond simply increasing qubit count, the company is leveraging high-throughput metrology to understand and optimise the performance of these systems, a crucial step towards fault-tolerant quantum computing. The recent work, detailed in a preprint released on arXiv, demonstrates the ability to analyse coherence distributions across an entire 3-inch wafer containing over 500 superconducting qubits.
This isn’t merely about scaling up fabrication; OQC’s innovation lies in extracting meaningful data from these large ensembles. “By measuring O(100) qubits on a single monolithic wafer, OQC demonstrates the ability to extract not only median coherence metrics but also to study spatial trends and coherence distributions across the wafer,” highlighting the power of statistical analysis. Bootstrapped sampling revealed that accurately determining minimum and maximum coherence values demands substantial sample sizes, reinforcing the need for large-N studies to refine research and development cycles.
Packages capable of supporting large arrays of high-coherence superconducting qubits are vital for the realisation of fault-tolerant quantum computers and the necessary high-throughput metrology required to optimise fabrication and manufacturing processes.
Oxford Quantum Circuits (OQC)
