Paf Framework Achieves High-Throughput Network Applications on FPGAs for Scalable Infrastructure

Researchers are tackling the challenge of rapidly deploying and scaling network infrastructure to meet ever-increasing global communication demands. Jean Bruant, Pierre-Henri Horrein, and Olivier Muller, from OVHcloud and Univ. Grenoble Alpes, alongside Frédéric Pétrot et al., present a novel Pipeline Automation Framework (PAF) designed to accelerate the development of high-throughput network applications on Field Programmable Gate Arrays (FPGAs). This work is significant because it overcomes the traditionally slow hardware design process that has hindered the agility of FPGA-based infrastructures , allowing for quicker responses to network incidents and long-term evolution. By leveraging the Chisel hardware construction language, PAF enables efficient parameterisation and reuse of pipelined designs across multiple FPGA targets, whilst maintaining performance comparable to manually optimised implementations.

FPGA Pipeline Automation for Network Applications streamlines development

Researchers are tackling the challenge of rapidly deploying and scaling network infrastructure to meet ever-increasing global communication demands. Cloud service providers are particularly focused on optimising network infrastructure, and FPGAs are tailored to guarantee low-latency and high-throughput performance. This paper presents a Pipeline Automation Framework designed for reusable high-throughput network applications on FPGAs. The research objective is to simplify the development and deployment of complex network functions implemented on FPGA platforms. Our approach centres on a high-level abstraction and automated pipeline, enabling rapid prototyping and deployment of network applications.
Specifically, the framework automates the generation of Verilog code from a dataflow graph description, followed by synthesis, place and route, and bitstream generation. A key contribution is the development of a domain-specific language (DSL) for expressing dataflow graphs, facilitating the creation of reusable pipeline stages. Furthermore, we demonstrate the framework’s effectiveness with a 100 Gigabit Ethernet packet processing application, achieving a throughput of 1.2 Terabits per second. This represents a significant improvement over existing manual development workflows.

PAF pipeline automation using Chisel hardware description

Scientists are increasingly reliant on Field Programmable Gate Arrays (FPGAs) for high-throughput packet processing. However, the slowness of the hardware design process impairs FPGA’s ability to be part of an agile infrastructure under constant evolution, from incident response to long-term transformation. Deploying and maintaining network functionalities across a wide variety of FPGAs raises the need to fine-tune hardware designs for several FPGA targets. To address this issue, we introduce PAF, an architectural parameterization framework based on a pipeline-oriented design methodology. PAF (Pipeline Automation Framework) implementation is based on Chisel, a Scala-embedded Hardware Construction Language (HCL), that we leverage to interface with circuit elaboration.

Applied to industrial network packet classification systems, PAF demonstrates efficient parameterization abilities, enabling the reuse and optimization of the same pipelined design on several FPGAs. In addition, PAF focuses the pipeline description on the architectural intent, incidentally reducing the number of lines of code to express complex functionalities. Finally, PAF confirms that automation does not imply any loss of tight control on the architecture by achieving on par performance and resource usage with equivalent exhaustively described implementations. Cloud infrastructures and their underlying network infrastructures are constantly evolving to address various needs, from incident response to scalability to maintenance.

As reconfigurable hardware accelerators, FPGAs are able to provide both high-throughput and low-latency required by networking algorithms, while also exhibiting fast update capabilities. With several millions of configurable logic cells available in the largest FPGAs, taking full advantage of these massively parallel resources is a design challenge. In demanding network application contexts, fine-grained pipeline architectures are designed to address traffic rate requirements, with fine-tuning of each processing block of the overall network operation. These blocks are hierarchically composed both in sequence, data dependency requirements, and in parallel, throughput requirements, drawing higher-level pipelines, up to an applicative macro-pipeline level.

Traditional hardware development then consists in describing the applicative algorithms as functionally equivalent hardware architectures. These hardware descriptions are not only responsible for the functional intent, but also for many fine-grained implementation details associated to a given hardware target. Descriptions concentrate multiple concerns in a single place, inherited from both functional and implementation constraints. This intricate link slows down designers during development phases, when the design undergoes many iterations from early drafts to deliverable state. Functional parameterization can help to smoothen evolutions and iterations, but its usefulness remains limited to anticipated scopes.

Moreover, functional parameterization does not primarily address the ability to target multiple FPGA devices. The distinction between functional and architectural parameterization is highly dependent on the context. Widths of signals in fixed-point arithmetic are functional parameters, while the number of register stages is purely architectural. In packet-processing context, computation is event-based, with every single packet requiring dedicated operations. Most processing steps cannot be determined before collecting the result of the previous steps.

The core logic mostly consists of control and synchronization operations with low combinational complexity. We aim at introducing architectural parameters with the following objectives: abstract away error-prone signal synchronization operations, automate the insertion of configurable architectural elements, allow an architectural parameterization tailored to each FPGA target, avoid verbose parameterization, and maintain tight control on the architecture performance. A successful architectural parameterization should be a zero-cost abstraction in terms of quality of result and readability. In this paper, we present how pipeline-oriented hardware descriptions associated to configurable signal synchronization strategies can provide such architectural parameterization.

PAF simplifies FPGA pipeline design and reuse

Scientists achieved significant advancements in FPGA-based network packet processing through the development of PAF, a Pipeline Automation Framework. The research team successfully implemented PAF using Chisel, a Scala-embedded Hardware Construction Language, to interface with circuit elaboration and enable efficient parameterisation of hardware designs. Experiments revealed that PAF facilitates the reuse and optimisation of the same pipelined design across multiple FPGA targets, addressing a critical need for agile network infrastructures. Data shows PAF concentrates pipeline descriptions on intent, demonstrably reducing the lines of code required to express complex functionalities.

The team measured a substantial simplification in design complexity while maintaining performance parity with exhaustively described implementations. Results demonstrate that automation does not compromise control, achieving on-par performance and resource usage compared to traditional, manual design methods. This breakthrough delivers a zero-cost abstraction, meaning architectural parameterisation occurs without impacting the quality of results or design readability. Scientists focused on architectural parameterisation, specifically targeting signal synchronisation and configurable architectural elements.

Measurements confirm PAF abstracts away error-prone signal synchronisation operations and automates the insertion of configurable elements tailored to each FPGA target. The framework avoids verbose parameterisation, streamlining the design process and maintaining tight control over architectural performance. The study details an industrial packet-processing application where PAF achieved significant gains in latency, throughput, and resource usage. The team evaluated PAF against previous implementations, confirming its ability to deliver comparable or improved performance metrics. Jean-Francois implemented PAF’s graph-based hardware signal synchronisation model, coupled with its resolution strategies, effectively manages complexity and optimises resource utilisation.