Monolayer Transistor Variability Model Accurately Predicts Current Fluctuations in Devices

A physics-based compact model accurately describes drain current fluctuations in monolayer graphene field-effect transistors. The research identifies carrier number and Coulomb scattering as key sources of variance, validated across multiple devices and bias conditions. A series resistance model further explains variance at high carrier densities.

The performance of field-effect transistors (FETs) is increasingly subject to subtle variations in electrical current, a phenomenon that limits the reliability and predictability of electronic devices. Understanding and modelling these fluctuations is therefore crucial for the development of next-generation transistor technologies, particularly those utilising novel materials like graphene. Researchers led by Nikolaos Mavredakis, Anibal Pacheco-Sanchez, Ramon Garcia Cortadella, Anton-Guimerà-Brunet, Jose A. Garrido and David Jiménez detail a physics-based compact model in their work, Physics-Based Compact Modeling for the Drain Current Variability in Single-Layer Graphene FETs, which accurately describes current fluctuations in graphene FETs. Their model identifies the physical mechanisms – specifically carrier number and Coulomb scattering – responsible for these variations and validates its predictions across a range of device sizes and operating conditions.

Variability in Graphene Field-Effect Transistors: A Physics-Based Compact Model

Recent research details a physics-based compact model that accurately characterises drain current ($I_D$) fluctuations in monolayer graphene field-effect transistors (GFETs). This addresses a critical need for thorough on-wafer variability assessment as GFET technology matures and seeks to improve device performance. The model explicitly incorporates physical mechanisms responsible for 1/f noise – a frequency-dependent fluctuation in electrical signals – to explain observed $I_D$ variance and ultimately enhance circuit reliability.

Specifically, the research identifies carrier number fluctuations and Coulomb scattering-induced mobility fluctuations as key contributors to $I_D$ variance, providing a deeper understanding of device behaviour. Carrier number fluctuation arises from random variations in the number of charge carriers within the channel. Coulomb scattering, a result of interactions between charge carriers and imperfections in the graphene lattice, affects carrier mobility – a measure of how easily carriers move through the material. The model localises these effects within the GFET channel, integrating their contributions along the channel length from source to drain to determine the total variance and predict performance variations. This approach offers a more nuanced understanding of the origins of variability than previous methods and allows for targeted optimisation strategies.

Experimental validation confirms the model’s accuracy across a statistical population of three solution-gated GFETs, demonstrating its practical utility and establishing its robustness. Measurements taken across a wide bias range, from strong p-type to strong n-type conditions – referring to the transistor operating in conditions favouring either hole (p-type) or electron (n-type) conduction – demonstrate the model’s predictive capability. The findings establish a direct link between fundamental physical mechanisms and observed device variability, providing a robust framework for predicting and mitigating performance fluctuations in GFET-based circuits.

The researchers also derive a model for series resistance-induced $I_D$ variance, highlighting its significant contribution at high carrier densities and improving the model’s completeness. Series resistance arises from the resistance of the graphene sheet and the contacts, limiting current flow. This addition enhances the model’s predictive capability across a wider range of operating conditions, improving its utility for circuit design and optimisation. This work provides a valuable tool for designers and manufacturers of GFET-based circuits, facilitating improved circuit design, enhanced performance prediction, and ultimately, more reliable GFET-based electronic devices.

The detailed understanding of variance mechanisms also guides optimisation strategies for GFET fabrication processes, allowing for targeted improvements in device performance and yield. Future work should focus on extending this model to encompass more complex GFET architectures, including those incorporating heterostructures – layered materials with differing electronic properties – or advanced channel materials. Investigating the impact of process variations on model parameters and refining the model to account for temperature dependence are also crucial next steps, ensuring its applicability across a wider range of operating conditions.

Expanding the validation to a larger and more diverse set of devices will further solidify the model’s reliability and general applicability, establishing its position as a standard for GFET characterisation.