Memristors Enhance In-Memory Computing with Regulated Current Control Architecture

Researchers developed a two-terminal memristor architecture utilising regulated current to precisely control conductance and eliminate issues arising from wire resistance and unwanted current leakage. This configuration, employing a 2T1R array, avoids potential divider effects and establishes a stable virtual ground for improved performance.

The pursuit of energy-efficient computation is driving research into novel memory technologies, with memristors – passive two-terminal devices exhibiting resistance that depends on past current – emerging as a strong contender. These devices offer the potential for in-memory computing, performing calculations directly within the memory itself, thereby reducing data transfer bottlenecks and power consumption. Researchers at Forschungszentrum Jülich and the University of Duisburg-Essen, led by Neethu Kuriakose, Arun Ashok, Christian Grewing, and André Zambanini, alongside Stefan van Waasen, detail a new architecture for controlling memristor conductance in their paper, “2T1R Regulated Memristor Conductance Control Array Architecture for Neuromorphic Computing using 28nm CMOS Technology”. Their work focuses on a two-transistor, one-resistor (2T1R) array designed to mitigate issues with signal interference and improve the precision of conductance control, crucial for applications in neuromorphic computing – a field aiming to mimic the structure and function of the human brain.

Memristor System Achieves Efficient Vector-Matrix Multiplication

Researchers have demonstrated a functional in-memory computing system utilising memristors, performing computations directly within the memory array and circumventing the limitations of conventional von Neumann architectures. The system employs a 2T1R (two transistors, one memristor) configuration, mitigating sneak path currents – a significant challenge in memristor crossbar arrays – and enabling more accurate analogue computations. This approach leverages memristor conductance as a variable resistance, directly proportional to input voltages, as defined by the equation:

[i = \sum(v_i g_{ij})]

where i represents output current, v_i input voltages, and g_ij the conductance of individual memristors.

The implemented system integrates a RISC-V processor for system control, configuration, and potential data pre/post-processing, alongside standard digital interfaces like SRAM and JTAG for debugging and testing. A key innovation lies in the regulated 2T1R architecture, which actively suppresses sneak paths by grounding both memristor terminals and facilitates precise conductance control through regulated current application. This regulated approach avoids the potential divider effect inherent in simpler crossbar designs, ensuring reliable and predictable operation, and ultimately enhancing computational accuracy. The chip occupies an area of 1.4 mm x 1.0 mm, demonstrating potential for high-density integration and scalability.

Traditional computing architectures suffer from limitations due to the physical separation of processing and memory, creating a bottleneck known as the von Neumann bottleneck. This restricts data transfer speeds and consumes significant energy, hindering the performance of computationally intensive tasks like machine learning and artificial intelligence. In-memory computing offers a potential solution by integrating computation directly within the memory array.

Memristors, or memory resistors, are passive two-terminal devices whose resistance depends on the history of current that has flowed through them. This property allows them to store information and perform computations simultaneously.

The regulated current source ensures accurate conductance modulation, critical for achieving the desired computational results. The system demonstrates significant energy savings compared to traditional digital implementations of vector-matrix multiplication (VMM) – a fundamental operation in many machine learning algorithms – highlighting the potential of in-memory computing for energy-efficient machine learning. VMM involves multiplying a vector by a matrix, a computationally intensive task and a key operation in neural networks.

The chip’s design addresses limitations of earlier memristor-based systems, such as the impact of wire resistance and virtual ground scenarios, enhancing overall performance and reliability. Wire resistance can significantly degrade signal integrity and reduce computational accuracy, while virtual ground scenarios can lead to unpredictable behaviour. The implemented design incorporates techniques to minimise wire resistance and ensure a stable ground potential, improving the overall performance and reliability of the system.

Future work will focus on scaling the array size to increase computational throughput and exploring advanced materials to further improve memristor performance. Increasing the array size will enable the system to handle larger and more complex computational tasks, expanding its applicability. Exploring advanced materials will improve memristor characteristics, such as switching speed, endurance, and linearity, further enhancing system performance and reliability.

Researchers also plan to investigate novel circuit architectures and computational algorithms to fully exploit the capabilities of memristor-based in-memory computing. Exploring different circuit architectures will optimise the system for specific computational tasks, maximising performance and energy efficiency. Developing novel computational algorithms will leverage the unique characteristics of memristors, enabling the implementation of advanced machine learning algorithms and artificial intelligence applications.

The development of memristor-based in-memory computing represents a step towards overcoming the limitations of traditional computing architectures. By integrating computation directly within the memory array, this technology promises new levels of performance, energy efficiency, and scalability. This research paves the way for a new generation of intelligent computing systems that can address the growing demands of the digital age.

The successful implementation of a regulated 2T1R architecture, coupled with the integration of a RISC-V processor and standard digital interfaces, provides a robust and versatile platform for exploring the full potential of memristor-based in-memory computing. Continued research and development efforts will focus on scaling the array size, exploring advanced materials, and developing novel circuit architectures and computational algorithms. These advancements will pave the way for the widespread adoption of memristor-based in-memory computing, transforming the landscape of computing and enabling a new era of intelligent systems.