Hybrid Encryption Accelerates Secure Data Analysis in the Cloud.

The increasing demand for data privacy necessitates advanced encryption methods, yet fully homomorphic encryption, which allows computation on encrypted data, often suffers from substantial computational overhead and ciphertext expansion. Researchers are now focusing on hybrid approaches, combining the efficiency of symmetric key encryption with the privacy benefits of homomorphic encryption. Yeonsoo Jeon, Mattan Erez, and Michael Orshansky, from The University of Texas at Austin, detail their work in ‘Presto: Hardware Acceleration of Ciphers for Hybrid Homomorphic Encryption’, presenting a hardware accelerator designed to improve the performance of two prominent ciphers, HERA and Rubato, used within these hybrid systems. Their implementation on a Virtex UltraScale+ FPGA demonstrates a significant increase in throughput, alongside reductions in both latency and energy consumption, compared to software-based implementations.

Hybrid Homomorphic Encryption (HHE) offers a pragmatic solution for deploying homomorphic encryption (HE), combining the efficiency of symmetric key cryptography with the privacy benefits of HE. This approach mitigates the ciphertext expansion inherent in traditional HE schemes, making it particularly suitable for client-server applications where data confidentiality is paramount. Recent research details a hardware accelerator designed to optimise the performance of two prominent HHE ciphers, HERA and Rubato, both built upon the CKKS homomorphic encryption scheme.

The design prioritises vectorisation and functional overlap within the cryptographic modules, substantially increasing data processing speeds. Crucially, the implementation exploits the transposition-invariance property of the MixColumns and MixRows functions – linear transformations used in many cryptographic algorithms – reordering intermediate states to eliminate operational bubbles during stream key generation and streamlining computations. This optimisation directly improves both latency and throughput. Researchers further decouple the random number generation (RNG) and key computation phases, effectively masking the latency of the RNG and shortening the critical path within first-in, first-out (FIFO) buffers, thereby enabling higher operating frequencies and boosting overall performance.

Implementation on a Xilinx Virtex UltraScale+ field-programmable gate array (FPGA) demonstrates substantial performance gains, validating the effectiveness of the proposed architecture. Both Rubato and HERA achieve a six-fold increase in throughput compared to their software counterparts, showcasing a significant acceleration in data processing capabilities. Rubato exhibits a five-fold reduction in latency, while HERA achieves a three-fold improvement, demonstrating the ability to process data with reduced delays. Beyond speed, the hardware implementations deliver significant energy savings, reducing consumption by seventy-five times for Rubato and forty-seven times for HERA, relative to software implementations, highlighting the potential for energy-efficient secure computations.

While the results demonstrate considerable performance gains, future work should focus on comparative analysis against other state-of-the-art homomorphic encryption accelerators, including those designed for different HE schemes such as BFV, CKKS, or TFHE, providing a comprehensive evaluation of the proposed design. A detailed power consumption analysis, alongside precise specification of the FPGA device used, would further strengthen the reproducibility and impact of the research, enabling other researchers to verify and build upon the findings.

Addressing potential security vulnerabilities, such as those arising from side-channel attacks – where information is leaked through physical characteristics like power consumption or timing – or fault injection, is also crucial for practical deployment, ensuring the robustness and integrity of the hardware implementation. Furthermore, investigating the scalability of the design to larger parameter sets and analysing the impact of potential errors in the hardware implementation on computational accuracy represent important avenues for future investigation, expanding the applicability and reliability of the proposed solution. Exploring alternative optimisation techniques and targeting different hardware platforms could also broaden the applicability of this work, paving the way for more versatile and efficient secure computation solutions.

These findings highlight the potential of hardware acceleration for HHE, enabling practical and efficient secure computation in various applications, including cloud computing, data privacy, and secure communication. Future work will focus on exploring alternative optimisation techniques, investigating the scalability of the design to larger parameter sets, and analysing the impact of potential errors in the hardware implementation. Additionally, researchers plan to investigate the implementation of the design on application-specific integrated circuits (ASICs) to further enhance performance and energy efficiency.

This research contributes to the growing field of homomorphic encryption by providing a practical and efficient hardware accelerator for HHE. The proposed design addresses the critical need for secure and efficient computation in various applications, paving the way for wider adoption of homomorphic encryption in real-world scenarios. By leveraging advanced techniques and demonstrating significant improvements in performance and energy efficiency, this work represents a significant step towards realising the full potential of homomorphic encryption.