QPU Micro-Kernels Enable PDE Solutions Via Shallow Circuits and Monte Carlo Estimation

Solving complex partial differential equations remains a significant challenge in scientific computing, and researchers continually seek more efficient methods. Stefano Markidis, Luca Pennati, and Marco Pasquale, along with colleagues at KTH Royal Institute of Technology, now present a novel approach using quantum processing units (QPUs) designed to accelerate these calculations. Their work introduces QPU micro-kernels, compact quantum circuits that perform localised updates within a computational stencil, effectively transforming the QPU into a sampling accelerator. This method bypasses the need to encode entire problems into deep quantum circuits, instead focusing on parallelising local updates and demonstrating improved accuracy and efficiency on benchmark equations such as the Heat and viscous Burgers’ equations, particularly with the Bernoulli micro-kernel implementation on actual quantum hardware.

Quantum Micro-Kernels Accelerate Stencil Computations

Researchers introduce QPU micro-kernels, a new technique for accelerating stencil computations, a common operation in many scientific applications. These micro-kernels are shallow quantum circuits designed to perform localized updates within a computational stencil, effectively acting as sampling accelerators and offering potential speedups over classical algorithms, particularly for large problems.

The team developed micro-kernels that consume only local inputs, such as neighboring values and coefficients, and execute a parameterized quantum circuit. These circuits report the average of a readout rule, and resource requirements, in terms of qubits and circuit depth, remain constant regardless of the overall grid size, making them easy to integrate with classical processors and parallelize across multiple grid points. Two versions were created: a Bernoulli micro-kernel, which encodes values as single-qubit probabilities, and a branching micro-kernel, which utilizes superposition and multi-controlled rotations.

Quantum Acceleration of Stencil Computations

This research explores the potential of quantum processing units to accelerate high-performance computing workloads, specifically focusing on stencil computations. The work emphasizes a hybrid approach, where quantum computers work alongside classical processors, tackling specific tasks where quantum acceleration is beneficial, and requires abstraction layers to simplify the use of quantum hardware for application developers.

Researchers are exploring various quantum algorithms relevant to these applications, including quantum linear solvers, quantum Monte Carlo methods, and amplitude estimation. A key challenge is mitigating errors inherent in current quantum hardware, and the team highlights the need for error mitigation techniques to achieve reliable results. The research aims to create a layered architecture that seamlessly integrates quantum accelerators into existing HPC workflows, promoting modularity, scalability, and fault tolerance.

Quantum Micro-Kernels Accelerate PDE Solutions

This work introduces QPU micro-kernels as a novel approach to solving partial differential equations, effectively offloading stencil computations from classical processors. Two realizations of these micro-kernels were created: a Bernoulli variant, which encodes values as single-qubit probabilities, and a branching variant, which utilizes superposition and multi-controlled rotations.

Testing on both simulated and real quantum hardware, including the IBM Brisbane quantum computer, demonstrated that both micro-kernels accurately reproduce expected update statistics. The Bernoulli realization exhibited lower errors on current hardware due to its simpler circuit structure and reduced susceptibility to gate errors. Researchers validated the method by applying it to the Heat equation and the viscous Burgers’ equation, commonly encountered in scientific computing. While current implementations rely on direct sampling, the team proposes future work incorporating Iterative Amplitude Estimation to potentially reduce the number of kernel invocations, acknowledging challenges related to circuit depth and applying this technique to multiple grid nodes simultaneously. The study also identified spatially non-uniform sampling errors, motivating the development of adaptive shot allocation strategies to optimize resource usage and improve accuracy by focusing sampling efforts on regions with high variability or small field magnitudes.