Better Photonic Chips Overcome Fabrication Limitations

Researchers are addressing a critical challenge hindering the widespread adoption of inverse-designed photonic integrated circuits: the difficulty of reliable, high-yield manufacturing. Hongjian Zhou from Arizona State University, Haoyu Yang from NVIDIA Corp., and Tianle Xu from Rensselaer Polytechnic Institute, working with colleagues at Arizona State University, NVIDIA Corp., and Rensselaer Polytechnic Institute, present a new workflow called PRISM, which stands for Photonics-Informed Inverse Lithography for Manufacturable Inverse-Designed Photonic Integrated Circuits. This collaborative effort introduces a data-efficient and optics-informed approach to mask optimisation, effectively bridging the gap between simulated performance and actual fabrication results. By synthesising informative calibration patterns and training a differentiable fabrication model, PRISM enables gradient-based optimisation that prioritises performance-critical features, ultimately promising to democratise the creation of scalable and high-yield photonic hardware.

Photonic chips promise revolutions in computing and communication, but building them has remained stubbornly difficult. A new technique addresses a key obstacle: translating complex designs into reliably manufactured components. This advance could unlock the potential of these devices by making high-performance photonic circuits readily scalable and accessible.

Scientists are increasingly focused on photonic integrated circuits (PICs) for interconnects and for computing and sensing workloads relevant to large-scale AI systems. Recent advances in photonic inverse design have demonstrated the ability to automatically synthesise compact, high-performance photonic components that surpass conventional, hand-designed structures, offering a promising path toward scalable and functionality-rich photonic hardware. However, the practical deployment of inverse-designed PICs is bottlenecked by manufacturability, as their irregular, subwavelength geometries are highly sensitive to fabrication variations, leading to large performance degradation, low yield, and a persistent gap between simulated optimality and fabricated performance.

Reduced calibration data enhances photonic device fabrication optimisation

Across multiple inverse-designed components fabricated using both electron-beam lithography and deep ultra-violet photolithography, PRISM demonstrably boosted post-fabrication performance and yield. Calibration area was reduced, alongside a decrease in turnaround time, enabling scalable and high-yield inverse-designed photonic hardware. Detailed analysis revealed that PRISM consistently achieved improved pattern fidelity, critical for maintaining optical performance after fabrication.

The core of PRISM’s success lies in its ability to synthesize compact calibration patterns, minimising the amount of fabrication data required for accurate model training, a substantial improvement over existing methods. Specifically, the system required significantly less data to build a reliable fabrication model, streamlining the optimisation process.

Once acquired, this data was used to train a grounded differentiable fabrication model, allowing for gradient-based optimisation of the mask design. At the heart of the fabrication model is a point spread function (PSF) described by a double-Gaussian, capturing both short-range forward scattering and long-range backscattering contributions. The parameters defining this function, α and β, representing characteristic scattering ranges, were precisely determined through calibration.

The weighting factor, η, defining the balance between forward and backscattering, was also accurately established. These parameters, essential for modelling electron-beam lithography, were refined through iterative optimisation. PRISM’s photonics-informed inverse mask optimisation proved particularly effective by prioritizing performance-critical features beyond simple geometry matching, creating masks that yielded devices with superior optical characteristics.

This approach addressed a key limitation of traditional lithography workflows, where geometric fidelity often fails to translate to functional performance in photonic circuits. The research showed a marked improvement in the consistency of sidewall angles after etching, a parameter directly impacting device performance. The model accurately predicted final resist profiles, including critical dimension and sidewall angle, from the aerial image.

This was achieved through a rate-based dissolution model, capturing effects such as resist contrast and diffusion. By accurately simulating these processes, PRISM enabled the creation of masks that were more resilient to fabrication variations.

Mitigating manufacturing-induced performance loss in inverse-designed photonic integrated circuits

Scientists are increasingly recognising photonic integrated circuits (PICs) as a foundational hardware platform for high-bandwidth communication, optical interconnects, and speed-of-light computing, with growing adoption in areas such as artificial intelligence (AI), sensing, quantum technologies, and scientific discovery. Despite this promise, the practical design and deployment of complex PICs at scale remain constrained by manufacturing realities, as fabricated wafers can deviate substantially from the intended design.

Subwavelength photonic structures, such as gratings and inverse-designed patterns, often suffer from huge geometric deviations leading to large performance degradation and malfunction, particularly in cascaded circuits where small component-level errors can accumulate into system-level failure. Inverse design has emerged as a powerful paradigm for automatically synthesising compact, high-performance components that surpass conventional hand-designed structures, offering a promising pathway to scalability breakthroughs in photonic hardware.

However, the fine-grained features enabling superior numerical performance often make inverse-designed layouts difficult to manufacture reliably at scale. In production-oriented deep ultraviolet (DUV) fabrication processes, such as 193nm technology, inverse-designed patterns can be considered infeasible due to severe distortions leading to near-zero yield.

Electron-beam lithography (EBL) can provide higher patterning resolution for laboratory demonstrations, but it remains costly and slow for high-volume manufacturing and still exhibits non-ideal distortion. DUV fabrication induces substantially larger figure of merit (FoM) degradation and a heavier worst-case tail than EBL across representative photonic devices, underscoring the manufacturability gap for inverse-designed layouts under DUV.

Wavelength division multiplexing transmission is jointly sensitive to lithography defocus and resist threshold, exhibiting a narrow high-performance process window. Consequently, inverse-designed photonics frequently remains difficult to translate from a theoretically plausible concept into deployable, repeatable hardware, especially when building larger circuits from many sensitive building blocks.

Designers often cope through expensive trial-and-error, imposing conservative design rules, sacrificing geometric degrees of freedom with smoothing, running extensive parameter sweeps, and iteratively re-taping-out designs based on sparse fabrication feedback. This workflow is slow, high-cost, expertise-heavy, and fundamentally at odds with the promise of inverse design, as it either sacrifices performance or fails to achieve robust yield.

A natural question arises as to why photonics cannot adopt the mature design-for-manufacturing (DFM) stack from electronic design automation (EDA). In electronics, foundries routinely apply optical proximity correction (OPC) and inverse lithography (ILT) to optimise masks and compensate for process effects. However, two obstacles prevent this direct transfer to photonics.

Firstly, photonic hardware performance relies on complicated light propagation behaviour, meaning mask correction objectives based purely on geometric similarity are insufficient, as “close geometry” does not imply “close function”. Optical response arises from nonlocal electromagnetic interactions and is often dominated by sensitivity-critical features, so errors in a small region can dominate performance even when global pixel-wise error is small.

Systematic geometric biases, such as globally biased over-/under-etch, can be especially detrimental because they coherently affect photonic function. A differentiable fabrication digital twin model is trained that generalises under limited data and provides stable gradients for mask optimisation across patterns. Inverse lithography is formulated as a function-preserving mask optimisation problem, introducing electromagnetic-field-aware objectives to preserve photonic function beyond geometry fidelity.

Across multiple inverse-designed components in EBL and 193nm DUV photolithography, PRISM significantly boosts post-fabrication device performance and yield with substantially lower calibration cost, unlocking manufacturable inverse-designed photonic hardware at scale. Photonic inverse design has emerged as a powerful paradigm for synthesising compact, high-performance photonic components by directly optimising electromagnetic objectives, enabling structures that outperform conventional hand-designed devices. A growing body of work has extended inverse design to account for fabrication constraints, including minimum feature size control, smoothing or regularisation of design variables, and robustness-aware objectives that mitigate sensitivity to process variation.

Manufacturing tolerance optimisation unlocks viable photonic integrated circuits

Scientists have long sought to create complex photonic circuits with the same ease and precision currently enjoyed in electronics. Yet, translating designs from simulation to reality has proven remarkably difficult. Unlike their electronic counterparts, photonic components are intensely sensitive to even minute manufacturing imperfections. These deviations, invisible to the naked eye, accumulate within a circuit, degrading performance and drastically reducing the number of working chips produced.

For years, this gap between ideal design and fabricated outcome has hampered the wider adoption of photonics, despite its potential for faster and more energy-efficient computing. Now, a new workflow called PRISM offers a potential solution by directly addressing the manufacturing process itself. Rather than simply aiming for geometrical perfection in a design, PRISM optimises the patterns used to create the chip, anticipating and correcting for likely fabrication errors.

This approach, informed by machine learning, allows for a more data-efficient calibration process, reducing the need for costly and time-consuming trial-and-error cycles. Once considered a major obstacle, the ability to reliably manufacture these intricate structures is now within closer reach. Challenges remain. The current system relies on training data gathered from specific fabrication processes, meaning a new process would require recalibration.

Beyond this, extending PRISM to even more complex, three-dimensional photonic structures will demand considerable computational power and algorithmic refinement. At the same time, the development of standardised fabrication models, shared across the industry, could accelerate progress for all. The future likely holds a convergence of these efforts, with AI-driven design tools and advanced manufacturing techniques working in tandem to unlock the full potential of photonic integrated circuits and reshape the landscape of data transmission and processing.