Lattice Surgery Aware Resource Analysis Enables Scalable Modular Quantum Circuit Mapping and Scheduling

The increasing complexity of building large-scale quantum computers drives exploration of modular architectures, where multiple smaller processing units work in concert. Batuhan Keskin from EPFL, Cameron Afradi from University of California, Berkeley, and Sylvain Lovis from EPFL, alongside colleagues, investigate the resource demands of such distributed systems. Their work presents a comprehensive framework that analyses the classical and quantum resources required to execute quantum circuits on a network of interconnected quantum cores. By developing algorithms for partitioning, mapping, and scheduling quantum operations, the team quantifies the trade-offs between inter-core communication, consumption of essential quantum states, and overall processing time, offering crucial insights for designing scalable and efficient modular quantum computers. This detailed analysis provides a vital step towards realising practical, large-scale quantum computation beyond the limitations of single-core designs.

Modular Quantum Computing and Scalability Challenges

Scientists are actively addressing the core challenge of building quantum computers large enough to solve practical problems. Current systems are limited by qubit count, and simply adding more does not guarantee improved performance. Maintaining qubit coherence and fidelity as the system scales is paramount, and researchers are exploring innovative approaches to overcome this hurdle. A dominant strategy is modular quantum computing, which involves breaking down a large quantum computer into smaller, interconnected modules, or chips. This approach offers advantages, including easier fabrication of higher quality modules, reduced wiring complexity, and potential fault tolerance through error correction and isolation of faulty modules.

Modularity provides a clear path towards scalability by allowing the system to grow through the addition of more modules. Researchers are investigating chiplet architectures, analogous to modern CPUs and GPUs, utilizing standardized, pre-fabricated modules. Developing high-fidelity, low-loss connections between these modules is critical, with ongoing work focusing on microwave networks and photonic interconnects utilizing light for quantum information transfer. Another promising avenue involves physically shuttling ions between modules to facilitate computation. Efficiently managing the flow of quantum information between modules through optimized communication protocols is also essential for maximizing performance.

Error correction is fundamental to building reliable quantum computers, and scientists are refining several techniques. Surface codes, well-suited for implementation on a two-dimensional lattice of qubits, are a leading approach. Lattice surgery allows manipulation of surface code qubits for logical operations and error correction, while transversal gates simplify the process. Newer approaches, such as hyperbolic Floquet codes, are also under investigation, alongside techniques like logical qubit teleportation. Developing software and algorithms tailored for scalable quantum computing is equally important.

Compiler optimization efficiently maps quantum algorithms onto modular architectures, optimizing qubit allocation, communication, and gate scheduling. Graph partitioning techniques divide quantum algorithms into subtasks executable on different modules. Machine learning, specifically reinforcement learning, is being employed to optimize qubit assignment and communication protocols, further enhancing system performance. Specific architectural approaches are also being explored, including multicore quantum computing utilizing multiple quantum cores for parallel computation, and distributed quantum computing distributing computations across multiple nodes. Trapped ion systems and superconducting qubit systems are both actively researched. This comprehensive research demonstrates that building scalable quantum computers is a complex undertaking requiring advances across numerous scientific and engineering disciplines.

Distributed Quantum Simulation and Resource Mapping

Scientists have engineered a comprehensive simulation framework to analyze resource consumption in distributed quantum computing (DQC) systems employing logical qubits. This work focuses on architectures where multiple cores each host logical data qubits and ancillas, connected by both classical and quantum communication channels. Researchers restricted the universal gate set to include Hadamard, T, S, and Pauli gates to model quantum circuits within this distributed system. They developed a method to translate any quantum circuit into this restricted gate set using the Qiskit software, followed by partitioning the qubits using the KaHIP graph partitioner to achieve balanced distributions across cores.

Following qubit partitioning, the team built an algorithm to map these qubit arrangements onto a two-dimensional mesh of quantum cores, formulated as a Quadratic Assignment Problem with Fixed Assignment (QAPFA) to minimize routing distance of two-qubit gates and travel distance of magic states. This approach prioritizes efficient communication and resource allocation. The framework schedules gates using an algorithm that carefully manages the timing of operations within the defined gate set, ensuring correct execution order and minimizing delays. The simulation reports detailed statistics quantifying both classical and quantum resources, including classical communications, EPR pairs, magic states consumed, and timing overheads associated with inter-core state transfers. This detailed analysis allows researchers to quantify the resources needed for scalable modular architectures and assess the feasibility of DQC with logical qubits. The study devised a routing system utilizing logical ancillas and smooth teleportation gates to schedule distant CNOT operations and efficiently distribute magic states.

Distributed Quantum Computing with Logical Qubits

Scientists have developed a comprehensive simulation framework for distributed quantum computing (DQC) utilizing logical qubits, enabling detailed analysis of both classical and quantum resource consumption. This work addresses the challenges of scaling quantum computers by exploring architectures where logical data and ancilla qubits reside on interconnected cores, communicating via classical and quantum channels. The team devised a routing system employing logical ancillas and smooth teleportation gates to efficiently transfer quantum states between logical qubits, crucial for executing distant two-qubit gates and distributing essential resources. A key innovation is the integration of a Magic State Factory (MSF) connected to a two-dimensional mesh of quantum cores, designed to supply the magic states required for universal computation, specifically for T and S gates.

Researchers introduced an optimization procedure for qubit-to-core and core-to-mesh placement, carefully considering the routing of both two-qubit gates and magic states to minimize resource overhead. This optimization directly impacts the efficiency of the entire system. Furthermore, the team created a scheduling algorithm that maximizes parallelism and pipelining of gates, taking into account the availability of logical qubits and the timing constraints of logical gates. This algorithm is critical for minimizing computation time and maximizing throughput. Experiments demonstrate the framework’s ability to quantify resource consumption, providing valuable insights into the trade-offs between quantum and classical resources in DQC architectures. The simulation framework allows for detailed analysis of the resources required for both quantum and classical networks-on-chip (NoC), providing a comprehensive understanding of system performance.

Joint Optimization of Qubit Placement and Gates

This work presents a comprehensive system for evaluating resource requirements in distributed quantum computing architectures utilizing logical qubits. Researchers developed a three-stage process beginning with a scheduling algorithm that routes logical states using a network of ancilla qubits. This was followed by emulation of classical traffic using a classical Network-on-Chip, providing detailed insight into classical resource consumption and timing. Finally, a robust mapping framework was designed to minimize two-qubit gates between cores and optimize the travel distance of magic states required for T and S gates.