AI Agent Swiftly Designs New Hardware for Unhackable Quantum-Era Encryption

Researchers are tackling the considerable challenges inherent in designing post-quantum cryptography (PQC) hardware, particularly the difficult conversion of reference codes into high-level synthesis (HLS) specifications. Buddhi Perera, Zeng Wang, and Weihua Xiao, from NYU Tandon School of Engineering, along with Mohammed Nabeel et al., present LLM4PQC, a novel agentic framework utilising large language models to automatically refactor PQC specifications and C code into synthesizable hardware descriptions. This work is significant because it substantially reduces the manual effort required for PQC hardware development and accelerates design-space exploration, offering a powerful and efficient route towards implementing complex cryptographic accelerators.

A significant impediment to PQC hardware development is the complex conversion of reference C code into high-level synthesis (HLS) specifications, a process traditionally demanding substantial manual effort.

This research introduces an automated pathway that refactors PQC specifications and C codes into HLS-ready, synthesizable C code, substantially reducing the need for manual intervention and enabling faster design-space exploration. The framework generates and rigorously verifies resulting register-transfer level (RTL) code through a hierarchical system of checks encompassing both C simulation and RTL simulation.

LLM4PQC addresses critical bottlenecks in PQC hardware implementation, including the scalability challenges associated with complex primitives like number theoretic transform (NTT) accelerators and wide memory interfaces. The system employs a feedback-driven approach, iteratively refining transformations based on compilation and simulation results, ensuring the generated hardware meets performance and area constraints.

Specifically, the work focuses on resolving HLS incompatibilities present in standard PQC kernels, such as calls to math.h functions, floating-point arithmetic, and dynamic runtime routines. This automated preprocessing is a key component of the overall workflow, preparing the code for efficient HLS conversion.

Case studies utilising NIST PQC reference designs, Kyber, Dilithium, and Falcon, demonstrate the efficacy of LLM4PQC in accelerating hardware development cycles. The framework’s contributions include LLM-driven preprocessing for HLS compliance, focusing on data-structure expansion, dynamic memory allocation, and constant initialisation.

Furthermore, the research presents a structured workflow for transforming PQC C code into synthesizable HLS-C, integrated with the Catapult tool for compilation, simulation, and synthesis. Empirical results confirm a significant reduction in manual effort and an improved ability to explore diverse design options for power, performance, and area optimisation.

LLM4PQC methodology for automated hardware synthesis of post-quantum cryptographic primitives

A 72-qubit superconducting processor forms the foundation of this research, facilitating the development of LLM4PQC, an agentic framework designed to synthesise post-quantum cryptography (PQC) hardware. The study addresses bottlenecks in converting PQC reference codes into high-level synthesis (HLS) specifications and scaling synthesis for complex PQC primitives such as number theoretic transform (NTT) accelerators.

LLM4PQC refactors high-level PQC specifications and C reference codes into HLS-ready C code, subsequently generating and verifying the resulting register-transfer level (RTL) code. The methodology comprises four distinct phases beginning with PQC subroutine extraction. GPT-5.2 is prompted to identify performance-critical functions within NIST PQC reference codebases, extracting these functions with minimal dependencies while preserving their functional interface.

Simultaneously, the LLM co-generates a verification infrastructure, including Known-Answer Tests (KATs), helper functions, and a test harness, enabling isolated compilation and functional validation of each subroutine at the C level. This KAT-based testing ensures functional equivalence before HLS conversion, reducing debugging complexity.

Following extraction, HLS preprocessing addresses issues arising from PQC implementations designed for portability rather than synthesis. Dynamic memory allocations, implemented using malloc and memcpy, are systematically transformed into static memory allocations via LLM-generated code, replacing dynamic calls with functionally equivalent static implementations.

The transformed C code undergoes compilation and validation against KATs, with error messages fed back to the LLM as corrective prompts for iterative refinement. A second preprocessing step targets runtime routines that compute and populate constant tables, replacing runtime computation with compile-time constants.

The LLM first detects initialisation functions, then generates a runner program to obtain fully initialised table values, emitting them as const array declarations in C syntax. Finally, the preprocessed C code is input into the LLM-driven C2HLSC framework for HLS-C generation and design-space exploration.

C2HLSC employs an iterative refinement process, transforming the input C code using error feedback from the synthesis tool and in-context learning examples. Each generated HLS-compatible C version is validated for functional correctness by comparing its outputs against the reference C implementation using KATs, ensuring accurate hardware acceleration.

LLM4PQC facilitates automated conversion of post-quantum cryptography C code for hardware synthesis

Scientists developed LLM4PQC, an agentic framework leveraging large language models to translate post-quantum cryptography (PQC) reference codes into high-level synthesis (HLS)-ready C code. The work addresses critical bottlenecks in PQC hardware design, specifically the conversion of C code to HLS specifications and the scalability of synthesis for complex primitives.

LLM4PQC integrates preprocessing transformations tailored for HLS-C, automated C-to-HLS transformation using a C2HLSC tool with Catapult, and a feedback loop driven by compilation and simulation failures to refine transformation outcomes. This research focuses on refactoring barriers commonly found in PQC kernels, including incompatible constructs like calls to math.h functions, floating-point arithmetic, and runtime routines for constant table construction.

The framework’s key contributions include LLM-driven preprocessing for HLS compliance, addressing challenges in data-structure expansion, dynamic memory allocation, and constant initialisation. A structured, feedback-driven workflow transforms PQC reference C code into synthesizable HLS-C, evaluated through an automated hardware design loop integrating C2HLSC and Catapult.

Empirical evaluation using established PQC algorithms, Kyber, Dilithium, and Falcon, and their core primitives demonstrates the framework’s effectiveness. These algorithms rely on subroutines such as the Number Theoretic Transform (NTT), sparse polynomial multiplication, SHAKE, Gaussian samplers, and Fast Fourier Transforms (FFT).

The study highlights the importance of hardware acceleration for computationally intensive PQC subroutines, which become performance bottlenecks on standard CPUs due to complex operations and irregular memory access patterns. LLM4PQC provides a powerful and efficient pathway for synthesizing complex hardware accelerators, reducing manual effort and accelerating design-space exploration.

LLM4PQC delivers synthesizable hardware for post-quantum cryptography with competitive FPGA resource usage

Researchers have developed LLM4PQC, an agentic framework utilising large language models to translate post-quantum cryptography reference implementations into synthesizable hardware accelerators. This framework refactors high-level specifications and C code into hardware description language (HDL)-ready code, generating and verifying the resulting designs through a compile-simulate-synthesize feedback loop.

Successful hardware generation was demonstrated for complex cryptographic kernels, including Falcon Sampler and number theoretic transform/fast Fourier transform primitives. Experimental results indicate that LLM4PQC effectively balances design productivity with hardware quality, achieving lower resource utilisation than several manually optimised baselines.

Although current designs exhibit a latency penalty compared to manual implementations, the approach surpasses existing LLM-based methods in both field-programmable gate array (FPGA) utilisation and latency. This confirms the benefits of an agentic, feedback-driven workflow over direct language model translation.

The authors acknowledge that, without specific guidance, the language model tends towards compact sequential code, potentially limiting hardware performance. Future research will focus on fine-tuning language models using high-level synthesis datasets and employing retrieval-augmented generation to incorporate verified HDL patterns during code creation. An LLM-driven evolutionary framework, coupled with pre-synthesis performance prediction models, is also envisioned to further accelerate design-space exploration.