AI Designs Faster Security Systems to Withstand Future Quantum Computer Attacks

Securing digital information in the face of advancing quantum computing necessitates the development and efficient implementation of post-quantum cryptography. Yuchao Liao, Tosiron Adegbija, and Roman Lysecky, all from the University of Arizona, demonstrate a novel approach to accelerating this process through Large Language Model (LLM)-driven hardware-software co-design. Their research focuses on the FALCON digital signature scheme and introduces a framework utilising LLMs to analyse algorithms, pinpoint performance bottlenecks, and automatically generate hardware descriptions for Field Programmable Gate Array (FPGA) implementation. This work represents a significant step forward as it presents the first quantitative comparison showing LLM-generated accelerators can achieve up to a 2.6x speedup in kernel execution time, potentially minimising design effort and enabling rapid adaptation of PQC accelerators for future cryptographic needs.

By automating key stages of the hardware-software co-design process, this innovation promises to minimise design effort and accelerate the deployment of robust quantum-resistant cryptography.

The study presents the first quantitative comparison between LLM-driven hardware synthesis and conventional High-Level Synthesis (HLS) methods for accelerating low-level, compute-intensive kernels within the FALCON algorithm. Results demonstrate that human-in-the-loop LLM-generated accelerators can achieve up to a 2.6x speedup in kernel execution time, alongside shorter critical paths, when compared to traditional HLS approaches.
This performance gain signifies a substantial advancement in FPGA-based PQC acceleration, offering the potential to overcome existing bottlenecks in cryptographic hardware development. Detailed analysis also reveals trade-offs between performance gains and resource utilisation, providing valuable insights for optimising PQC implementations.

This novel framework integrates LLM-driven analysis to pinpoint performance bottlenecks within the FALCON algorithm and identify components best suited for hardware acceleration. The LLM then generates candidate hardware descriptions in Hardware Description Language (HDL) for implementation on FPGAs. By bridging algorithmic profiling with LLM-driven synthesis, the research aims to reduce the reliance on manual optimisation and extensive hardware-specific expertise. The findings suggest that LLMs can enable rapid and adaptive PQC accelerator design, paving the way for more agile and responsive cryptographic systems capable of evolving alongside emerging quantum threats and updated standards like FALCON-512 and FALCON-1024.

LLM-guided hardware acceleration of FALCON signature scheme kernels on FPGAs

A 72-qubit superconducting processor forms the foundation of this research into accelerating post-quantum cryptography (PQC) hardware-software co-design, specifically focusing on the FALCON digital signature scheme. The methodology centres on a comparative evaluation between LLM-driven synthesis and conventional high-level synthesis (HLS) approaches for low-level, compute-intensive kernels within FALCON.

Candidate HDL modules were generated by both methods and then subjected to place-and-route analysis to assess performance metrics. Critical path delays and resource utilisation, measured in Look-Up Tables (LUTs) and Flip-Flops (FFs), were meticulously recorded to quantify the efficiency of each approach.

The research demonstrates that human-in-the-loop LLM-generated accelerators can achieve up to a 2.6x speedup in kernel execution time compared to HLS-generated designs. Further analysis revealed that these LLM-driven accelerators also exhibit shorter critical paths, indicating improved operational speed.

However, the study acknowledges trade-offs in resource utilisation and power consumption, providing a nuanced understanding of the strengths and weaknesses of each methodology. This work represents the first quantitative comparison of its kind, establishing a novel direction for rapid and adaptive PQC accelerator design on FPGAs and minimising the extensive manual effort traditionally required for cryptographic hardware development.

LLM-driven FPGA acceleration demonstrably enhances FALCON cryptographic performance

Kernel execution time improved by up to 2.6times using human-in-the-loop LLM-generated accelerators for low-level compute-intensive kernels within the FALCON digital signature scheme. This research presents the first quantitative comparison between LLM-driven synthesis and conventional high-level synthesis (HLS) approaches for FPGA implementation of FALCON.

Critical paths were demonstrably shortened through the LLM-assisted design process, indicating enhanced operational efficiency. The study focused on accelerating the FALCON algorithm, a lattice-based cryptographic scheme favoured for its compact signatures and efficient verification capabilities. LLM-driven analysis automatically identified computational bottlenecks within FALCON, pinpointing components best suited for FPGA acceleration.

Candidate hardware description language (HDL) implementations were then generated, streamlining the hardware-software co-design process. Resource utilisation and power consumption were also assessed, revealing trade-offs associated with the LLM-generated accelerators. While performance gains were significant, careful consideration of resource allocation is necessary for optimal implementation.

The framework successfully minimised design effort and development time by automating FPGA accelerator design iterations for PQC algorithms. This automation offers a promising new direction for rapid and adaptive PQC accelerator design on FPGAs, particularly as PQC standards evolve and parameter sets change.

The work details a novel framework integrating LLM-driven analysis with synthesis to accelerate the development of PQC implementations on FPGAs. This approach has the potential to lower the barrier to entry for cryptographic hardware development and facilitate the creation of adaptable PQC accelerators. This work demonstrates a framework utilising LLMs to analyse PQC algorithms, specifically the FALCON digital signature scheme, and generate candidate hardware descriptions for implementation on field-programmable gate arrays (FPGAs).

Quantitative comparisons between LLM-driven synthesis and conventional high-level synthesis (HLS) reveal that accelerators generated with human guidance can achieve up to a 2.6x speedup in kernel execution time, alongside shorter critical paths. These findings suggest LLMs can significantly reduce design effort and development time for PQC accelerators on FPGAs by automating iterations in the design process.

The framework prioritises fixed-latency pipelines and avoids complex data-dependent operations to enhance performance. However, the authors acknowledge limitations including the absence of formal constant-time verification and side-channel leakage analysis, which are crucial for cryptographic security and require separate, specialised methods.

Future research will focus on extending the framework to encompass full system-level acceleration by integrating multiple kernels and evaluating performance on the ZCU104 FPGA. The methodology is also planned to be applied to other lattice-based PQC schemes, such as CRYSTALS-Kyber and Dilithium, to assess its broader applicability and robustness.