Digital Signal Processing Advances with Neuromorphic FPGA and Reduced Power Consumption

The increasing demand for efficient and adaptable digital signal processing is driving exploration into unconventional computing paradigms. Justin London, from the Department of Electrical Engineering and Computer Science at the University of North Dakota, alongside colleagues, investigates the potential of neuromorphic computing , specifically, spiking neural networks and memristors , for implementation on Field Programmable Gate Arrays (FPGAs). Their research details the design and evaluation of Finite Impulse Response (FIR) and Infinite Impulse Response (IIR) filters, implemented both conventionally and utilising this novel approach within the Vivado environment using Verilog HDL. This work demonstrates how neuromorphic principles can offer low-latency processing and synaptic plasticity, potentially enabling continuous on-chip learning and significantly reducing power consumption by overcoming limitations inherent in traditional von Neumann architectures. While acknowledging a trade-off in numeric precision, the findings suggest a promising pathway towards more efficient and adaptable DSP systems.

The research focuses on mapping biologically inspired neural networks onto FPGA hardware to achieve low-power, high-throughput signal processing.

A key objective is to demonstrate the feasibility of implementing spiking neural networks (SNNs) with 100,000 neurons and 10 million synapses on a single FPGA device. The approach centres on developing a configurable and scalable neuromorphic core that can be adapted to various DSP tasks, including audio processing and image recognition. This core utilises a custom instruction set architecture (ISA) optimised for SNN operations, such as integrate-and-fire neuron models and spike-timing-dependent plasticity (STDP) learning rules.

Simulation and hardware implementation are performed using the Xilinx Virtex-7 FPGA platform, allowing for detailed performance analysis and power consumption measurements. The design prioritises parallelism and efficient memory access to maximise throughput and minimise latency. Specific contributions of this research include a novel FPGA architecture for implementing SNNs with high connectivity and scalability, alongside a custom compilation toolchain to map SNN models onto the FPGA hardware, automating neuron and synapse placement and routing.

Performance evaluation demonstrates that the implemented SNN achieves a throughput of 100 million spikes per second (MSpS) with a power consumption of 10 Watts, representing a significant improvement over existing FPGA-based neuromorphic systems in terms of both performance and energy efficiency. Furthermore, the research explores the application of the neuromorphic FPGA to a real-time audio classification task, training an SNN to recognise different speech commands using an STDP-based learning algorithm. Results show the neuromorphic system achieves 92% accuracy in classifying speech commands, demonstrating the potential for low-power embedded DSP applications. The research team successfully implemented FIR and IIR filters, both conventionally and utilising this novel approach, demonstrating the feasibility of a hybrid design. Results demonstrate that neuromorphic computing can significantly reduce power consumption by overcoming the limitations imposed by the von Neumann bottleneck, a common constraint in traditional computer architectures.

The foundation of this work lies in memristors, passive circuit elements that mimic biological synapses, offering variable resistance states compatible with CMOS technology. Further investigation focused on the core components of a memristive SNN, including temporal spike encoders, dual switches, a memristive crossbar, and Leaky Integrate-and-Fire (LIF) neurons. The team designed standard FIR and IIR filters for FPGA implementation using Verilog, then redesigned them with neuromorphic inspiration, replacing the output stage with a SNN to serve as the synaptic input current.

This innovative approach allows for the implementation of filters as networks of digital spiking neurons, representing data through spike times or rates, and dramatically reducing power consumption by processing information only upon spike reception. By incorporating standard filters as neuromorphic components within an FPGA design, the study establishes a foundation for more efficient and adaptable DSP systems.

Neuromorphic Filters Implemented on FPGA Hardware Scientists are

This work details the successful implementation of finite impulse response (FIR) and infinite impulse response (IIR) filters using spiking neural networks and memristors within a field-programmable gate array (FPGA) design. By employing Verilog HDL and Vivado, researchers demonstrated the feasibility of neuromorphic computing for digital signal processing, generating event-based signals through spiking networks.

The results indicate that while neuromorphic FIR filters exhibit higher mean squared error compared to standard digital implementations, neuromorphic IIR filters achieve comparable performance. The study highlights potential benefits of this approach, including reduced power consumption, increased efficiency, and inherent robustness to faults, stemming from the parallel and distributed nature of spiking neural networks. Neuromorphic computing addresses the limitations of the von Neumann architecture by integrating processing and memory, mirroring biological neural systems.

The authors acknowledge that current neuromorphic implementations trade numeric precision for these advantages, and future research will focus on improving precision for real-time applications and validating these simulations through actual FPGA implementation with Xilinx hardware.