Surface Codes Architect Scalable Trapped Ion Quantum Computers with up to 60 Qubits

Trapped ion qubits represent a leading technology in the race to build practical quantum computers, but scaling up these systems to the thousands of qubits needed for complex calculations remains a significant challenge. Scott Jones and Prakash Murali, both from the University of Cambridge, and their colleagues address this challenge by investigating how to efficiently implement error correction, a crucial step towards fault-tolerant quantum computation, on a promising modular architecture known as the Charge-Coupled Device. Their work focuses on surface codes, a standard error correction scheme, and demonstrates a new compilation method that dramatically improves the speed of logical operations, outperforming existing techniques by a factor of 3. 8. Importantly, the team reveals that surprisingly, small ion traps, containing only a few qubits, offer the best balance between performance and hardware efficiency, a finding that challenges previous assumptions and provides valuable guidance for the design of future, scalable quantum computers.

Trapped Ions and Quantum Computing Leaders

Several organizations are at the forefront of quantum computing research, particularly in the field of trapped ion technology. Quantinuum, formed by the merger of Honeywell Quantum Solutions and Cambridge Quantum Computing, is a leading company in this area. Researchers at the Universität Innsbruck in Austria, specifically within the Quantum Optics and Spectroscopy group, are also making significant contributions. Other universities, including those at Maryland, Harvard, and MIT, are actively involved through their research programs. Major technology companies, such as Microsoft with its Azure Quantum platform, are also investing heavily in quantum computing. These efforts are complemented by work at national laboratories, like the National Institute of Standards and Technology (NIST), which often collaborate with academic institutions. This landscape reflects both competition between companies and collaboration across academia and industry, all focused on advancing trapped ion quantum computing.

Surface Code Compilation for Modular QCCD Architectures

Scientists are developing modular quantum computers using trapped ion qubits and a Quantum Charge-Coupled Device (QCCD) architecture, aiming to overcome the limitations of current systems. This work addresses the challenge of scaling quantum computers while maintaining acceptable error rates, necessitating quantum error correction (QEC) to create robust logical qubits. Researchers are implementing surface codes, a standard QEC scheme, on QCCD systems to optimise architectural parameters for scalability. To evaluate different QCCD designs, the team developed a compilation method that translates surface code circuits onto diverse architectures.

This compiler significantly outperforms existing tools, accelerating logical clock speed by a factor of 3. 8. The compilation process maps logical qubits to the hardware and implements instructions using fundamental QCCD operations, respecting hardware constraints. This allows systematic exploration of the design space, considering factors like trap capacity and communication topology. Experiments involved detailed modelling of QCCD systems, including electrode configurations and time-varying signals for ion positioning. Surprisingly, the research demonstrates that small traps, housing only two ions, are ideally suited for both performance and hardware efficiency, challenging prior assumptions and informing future quantum computer design.

Two-Ion Traps Boost Quantum Compilation Speed

Researchers have achieved a breakthrough in designing scalable quantum computers using trapped ion qubits and surface code error correction. This work demonstrates how to efficiently implement surface codes on a Charge-Coupled Device (QCCD) architecture, a promising path towards building larger and more reliable quantum processors. The team developed a near-optimal compilation method that improves logical clock speed by a factor of 3. 8 compared to existing QCCD compilers, significantly enhancing the speed of quantum computations. A key finding challenges prior intuition, demonstrating that small traps containing only two ions are surprisingly ideal for both performance and hardware efficiency.

This result suggests a shift in design strategy, potentially simplifying the construction of future quantum systems. The compilation method effectively maps clusters of entangled qubits to traps, minimizing communication overhead and ensuring that qubits involved in the same operations are located close to each other. Detailed analysis of operation timings reveals that a two-qubit MS gate takes 40 microseconds, while ion rotation requires 5 microseconds. Measurement operations take 400 microseconds with low infidelity, and qubit reset takes 50 microseconds with similarly low error rates. Ion shuttling, a crucial operation for moving qubits between traps, takes 5 microseconds. The team’s modelling, using simulations and realistic noise models, allows for accurate prediction of logical error rates and resource requirements for surface code implementation on QCCD systems, representing a crucial step towards building practical, fault-tolerant quantum computers.

Efficient Surface Code Compilation on QCCD Architecture

This research demonstrates a pathway towards building larger, more reliable quantum computers using trapped ion qubits. Current quantum devices are limited in size and prone to errors, hindering their ability to solve complex problems. To overcome these limitations, scientists are exploring modular architectures and error correction techniques that require multiple physical qubits to create a single, robust logical qubit. This work investigates how to efficiently implement a standard error correction scheme, known as surface codes, on a specific modular architecture called a Charge-Coupled Device (QCCD).

The team developed a new method for compiling quantum circuits onto the QCCD system, achieving a significant improvement in speed compared to existing techniques. Surprisingly, the results indicate that using small traps, capable of holding only two ions, offers the best balance between performance and hardware efficiency. This finding challenges previous assumptions that larger traps would be preferable and provides valuable guidance for designing future quantum computers. The research highlights the importance of carefully co-designing the hardware architecture with the requirements of error correction, paving the way for scalable and practical quantum computation.