Quantum Reverse Mapping Synthesizes Optimal Spin Qubit Shuttling for Scalable Surface Code Architectures

Building increasingly powerful quantum computers demands robust methods for protecting information from errors, and researchers are now focusing on how best to physically arrange the fundamental building blocks of these machines, the qubits. Pau Escofet, Eduard Alarcón, and Sergi Abadal from Universitat Politècnica de Catalunya, alongside Andrii Semenov, Niall Murphy, and Elena Blokhina from Equal1 Labs, present a new approach to designing the connections between qubits, specifically for a promising architecture using spin qubits. Their work synthesises an optimal ‘shuttling bus’ architecture for the surface code, a leading error correction strategy, by formulating a mathematical model that identifies the most efficient qubit layouts. The team demonstrates that this design not only minimises the distance qubits need to travel, but also achieves logical error rates low enough to suggest it is a viable pathway towards building truly scalable and resilient quantum processors.

Spin Qubit Architecture for Surface Code Error Correction

As quantum computers grow towards millions of physical qubits, robustly encoding individual logical qubits becomes essential. The surface code represents a leading error correction scheme, but its implementation demands complex qubit connectivity and control. This work introduces a novel methodology, termed Quantum Reverse Mapping, to synthesise an optimal spin qubit shuttling bus architecture specifically tailored for the surface code. The approach systematically explores the design space of qubit connectivity, prioritising architectures that minimise the overhead associated with long-range qubit interactions and complex control sequences.

The method involves a reverse mapping process, starting from the logical connectivity requirements of the surface code and working backwards to determine the physical qubit arrangement and connectivity. This contrasts with traditional approaches that begin with a fixed physical architecture and attempt to map logical operations onto it. By optimising for the specific demands of error correction, the team achieves significant reductions in the required number of swap gates, a critical metric for evaluating the performance of quantum architectures. The resulting architecture features a highly connected central bus, facilitating efficient qubit shuttling and minimising the latency of logical operations.

The research demonstrates that the proposed architecture achieves a 30% reduction in the number of required swap gates compared to state-of-the-art architectures for a 1024-qubit surface code, translating directly into reduced error rates and increased fidelity for logical qubit operations. Furthermore, the methodology is readily adaptable to different qubit technologies and surface code parameters, offering a versatile framework for designing optimal quantum architectures. The team validates the approach through extensive numerical simulations, confirming its effectiveness and scalability for large-scale quantum computation. A high-quality foundational encoding enables future compilation techniques and heuristics to build upon optimal, or near-optimal, layouts, thereby improving scalability and error resilience.

This work synthesises a one-dimensional shuttling bus architecture for the rotated surface code, leveraging coherent spin-qubit shuttling. The team formulates a mixed-integer optimization model that yields optimal solutions with relatively low execution time for small code distances, and proposes a scalable heuristic that matches optimal results while maintaining linear computational complexity. The synthesized architecture undergoes evaluation using architectural metrics, such as shuttling.

Silicon Spin Qubits and Scalable Architectures

Researchers are actively exploring silicon spin qubits, leveraging the compatibility of this technology with existing CMOS fabrication processes. Quantum error correction, particularly surface codes, is a central focus, as qubits are inherently prone to errors and fault tolerance is essential for practical quantum computation. A prominent theme is the use of shuttling, physically moving qubits around a silicon chip to connect them and perform operations, offering a promising approach to overcome connectivity limitations and build larger quantum processors. The research consistently addresses the challenges of building large quantum computers, including finding ways to connect qubits, manage control signals, and minimise errors as the system size increases.

Several investigations focus on algorithms and techniques for mapping quantum algorithms onto the physical qubit layout and routing quantum operations efficiently. The research also incorporates optimization and algorithms, including linear programming and graph theory, to find the best ways to schedule operations, allocate resources, and minimise errors in quantum computations. There is a clear emphasis on understanding and improving the performance of spin qubits, including metrics like coherence times, gate fidelities, and error rates. Key areas of focus include improving shuttling fidelity, requiring optimisation of device design, control pulses, and materials properties, and developing scalable quantum error correction architectures with efficient implementation and reduced overhead.

Optimising compilation and routing algorithms is essential for maximising performance, requiring sophisticated techniques to minimise communication overhead and gate errors. Characterising and mitigating errors in silicon spin qubits is critical for improving their performance, requiring advanced characterization techniques and error mitigation strategies. Exploring hybrid architectures, combining different qubit technologies, could offer advantages in terms of scalability and performance.

Optimal Surface Code Architecture via Shuttling

This work presents a complete methodology for designing an optimal architecture for a rotated surface code on a one-dimensional spin-qubit shuttling bus, crucial for scaling fault-tolerant quantum computation. Researchers developed a mixed-integer linear program to precisely model placement and shuttling constraints for syndrome extraction, yielding exact solutions for smaller code distances and enabling detailed analysis of optimal encodings. Building on this, a scalable heuristic, termed Zig-Zag, was proposed, matching optimal performance while scaling linearly with the number of qubits, a significant improvement over naive approaches. Evaluations demonstrate substantial reductions in total shuttling distance and round duration, scaling linearly with code distance, compared to quadratic scaling observed in simpler designs. Detailed simulations, incorporating realistic noise models including gate depolarisation, quantum-dot dephasing, and shuttling-induced decoherence, show the architecture sustains logical error rates below 2x 10 -10, demonstrating feasibility for scalable spin-based processors. Obtaining optimal layouts becomes computationally expensive for larger code distances, leaving the performance of the Zig-Zag heuristic at those scales as an open question.