Low-cost Racetrack Cache, Utilising Data Compression, Achieves High Reliability Despite 1% Stochastic Errors and 11.3x Density Gains

As computing systems demand ever-increasing memory capacity and speed, conventional SRAM-based cache memory faces significant limitations, particularly as transistors shrink in size. Elham Cheshmikhani from Shahid Beheshti University, Fateme Shokouhinia from Simon Fraser University, and Hamed Farbeh from Amirkabir University of Technology address this challenge by investigating Racetrack Memory, a promising non-volatile memory technology with high density and performance comparable to SRAM. Their research tackles the inherent reliability issues of Racetrack Memory, which is prone to multiple-bit errors during data storage and shifting, by cleverly exploiting the predictable patterns in data values. The team demonstrates that compressing data allows them to reserve a substantial portion of the cache for robust error-correcting codes, significantly improving the system’s resilience to failures without increasing hardware costs or substantially impacting performance, achieving over eleven times improvement in mean-time-to-failure with minimal overhead.

Low-Cost Error Correction for Racetrack Memory Caches

Scientists have developed a novel scheme to improve the reliability of Racetrack Memory (RTM) when used as a Last-Level Cache (LLC). RTM, a promising technology for high-density and fast memory, is susceptible to errors caused by data shifting and the behavior of its magnetic tunnel junctions. The team addressed this challenge by combining data compression with strong Error-Correcting Codes (ECCs), leveraging data locality to free up space for more robust ECCs without increasing overall storage requirements. The researchers evaluated their scheme using detailed simulations with the gem5 simulator and the SPEC CPU 2017 benchmark suite.

Results demonstrate a significant improvement in cache reliability, with the mean-time-to-failure increasing by an average factor of 11. 3x compared to systems using conventional error correction, achieved with minimal performance impact and less than 1% overhead in hardware requirements. This makes the proposed scheme a practical and efficient solution for building dependable RTM-based memory systems.

Value Locality Enables Robust RTM Caching

Recognizing that RTM offers high density and performance but is prone to multiple-bit errors due to its unique structure and data shifting, scientists pioneered a method that leverages value locality to compress incoming data blocks. This effectively frees up cache lines for storing the data redundancy needed for robust ECCs, achieving a significant breakthrough in the reliability of Racetrack Memory (RTM) caches. Detailed simulations, using the gem5 full-system simulator, confirmed the effectiveness of this scheme, demonstrating an 11. 3x enhancement in cache reliability with less than 1% hardware and performance overhead. This achievement surpasses existing techniques, offering a practical pathway toward building more robust and dependable RTM-based caches for future computing systems.

Value Locality Boosts Racetrack Memory Reliability

Scientists developed a novel scheme that leverages value locality within data to compress information and free up cache blocks for robust error correction, without increasing storage requirements. This delivers a significant breakthrough in the reliability of Racetrack Memory (RTM) for use as a Last-Level Cache (LLC), demonstrating an 11. 3x enhancement in the mean-time-to-failure (MTTF) of the RTM-based LLC compared to systems protected by conventional Single-Error Correction and Double-Error Detection (SEC-DED) codes. The work addresses inherent reliability issues in RTM, stemming from domain shifting and the magnetic tunnel junction (MTJ) structure used for data storage. Detailed simulations, using the gem5 full-system simulator and the SPEC CPU2017 benchmark suite, confirmed the substantial improvement in reliability with less than 1% overhead in both hardware requirements and overall performance, confirming the viability of RTM as a strong contender for next-generation cache memory.

Compression Boosts Racetrack Memory Reliability

This research presents a novel approach to enhancing the reliability of Racetrack Memory (RTM) caches, addressing critical limitations in nanoscale computing. The team successfully demonstrates a method for mitigating multiple-bit errors, a significant challenge for RTM, without increasing storage overhead, stemming from the innovative application of data compression techniques which free up cache lines to accommodate stronger error-correcting codes. The study demonstrates a substantial improvement in cache reliability, achieving an average 11. 3x enhancement in mean-time-to-failure with minimal performance and hardware costs, less than 1% overhead. This outcome represents a significant advancement over existing methods, and paves the way for denser and more reliable caches based on RTM technology.